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ADT7473
Table 67. FAN TACHOMETER LIMIT REGISTERS (Note 1)
Register Address
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
TACH1 Minimum Low Byte
TACH1 Minimum High Byte/Single-channel ADC Channel Select
TACH2 Minimum Low Byte
TACH2 Minimum High Byte
TACH3 Minimum Low Byte
TACH3 Minimum High Byte
TACH4 Minimum Low Byte
TACH4 Minimum High Byte
Power-On Default
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
1. Exceeding any of the TACH limit registers by 1 indicates that the fan is running slowly or has stalled. The appropriate status bit is set in
Interrupt Status Register 2 to indicate the fan failure. Setting the Configuration Register 1 Lock bit has no effect on these registers.
Table 68. REGISTER 0 X55 ? TACH 1 MINIMUM HIGH BYTE (POWER-ON DEFAULT = 0XFF)
Bit No.
<4:0>
<7:5>
Mnemonic
Reserved
SCADC
R/W
Read-only
R/W
Description
These bits are reserved when Bit 6 of Configuration Register 2 (0x73) is set (single-channel
ADC mode). Otherwise, these bits represent Bits <4:0> of the TACH1 minimum high byte.
When Bit 6 of Configuration Register 2 (0x73) is set (single-channel ADC mode), these bits
are used to select the only channel from which the ADC makes measurements. Otherwise,
these bits represent Bits <7:5> of the TACH1 minimum high byte.
Table 69. PWM CONFIGURATION REGISTERS
Register Address
0x5C
0x5D
0x5E
R/W (Note 1)
R/W
R/W
R/W
PWM1 Configuration
PWM2 Configuration
PWM3 Configuration
Description
Power-On Default
ADT7473: 0x82
ADT7473 ? 1: 0x62
ADT7473: 0x82
ADT7473 ? 1: 0x62
ADT7473: 0x82
ADT7473 ? 1: 0x62
1. These registers become read-only when the Configuration Register 1 Lock bit is set. Any further attempts to write to these registers have
no effect.
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